This invention relates to twin well methods of forming CMOS integrated circuitry.
Typical CMOS circuitry fabrication includes several major process operations, with each operation requiring several steps and sub-steps. In each sub-step, several events could result in defective CMOS transistors, for example, substrate breakage, substrate warping, process variation, process defects and masking defects. The higher the number of sub-steps or steps, the higher the potential that a semiconductor substrate will not result with operable circuitry. Accordingly, the semiconductor processing industry is continually striving to reduce the number of processing steps, including masking steps.
CMOS circuitry includes PMOS transistor devices and NMOS transistor devices formed proximate each other over a semiconductor substrate. A component of each device includes a well structure in the semiconductor substrate. The PMOS devices are formed in n-wells while NMOS devices are formed in p-wells. One conventional method for forming the wells is a xe2x80x9ctwin-wellxe2x80x9d method. A semiconductor substrate is cut from an ingot and provided by a silicon ingot supplier. Typically, the semiconductor substrate received is pxe2x88x92 doped.
Two separate masking steps provide the p-well and n-well within the pxe2x88x92 doped substrate. The substrate is initially masked so that one of the desired p-well or n-well regions is masked while the other is unmasked. The desired implant is then conducted into the unmasked region to form the desired well. The process is then reversed with the just implanted region masked, and the other region unmasked and subjected to the opposite type dopant implant.
The transistor gates are typically formed after the well implants previously described and includes all the gate structures to be heavily n+ doped polysilicon for both the PMOS and NMOS devices. However, high performance CMOS devices, such as SRAMs and EDRAMs, may include p-type polysilicon gates for the PMOS devices and n-type polysilicon gates for the NMOS devices. To provide these gate structure designs, two masking steps are performed. One is for the p-type implant for the PMOS devices and one is for the n-type implant for the NMOS devices. Combine these two masking steps with the two masking steps previously discussed for xe2x80x9ctwin-wellxe2x80x9d formation and at least four masking steps are performed to implant the wells and gates during CMOS transistor fabrication.
Furthermore, each masking step has inherent and unique problems, particularly alignment accuracy during application of masking material. If the masking material is not aligned properly, one conductivity material in the PMOS devices may overlap another conductivity material in the NMOS devices effectively rendering the devices useless. For example, the p-type polysilicon gate for the PMOS device and n-type polysilicon gate for the NMOS device previously discussed are in such close proximity that the masking steps poses process limitations for CMOS fabrication. As the spacing between the PMOS and NMOS devices diminishes, alignment tolerances decrease thereby increasing the difficulty of aligning the masking material.
In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps.
In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.
In yet another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes depositing a transistor gate layer of a semiconductive material over a semiconductor substrate. After depositing the transistor gate layer and in one masking step, effectively masking a first substrate area configured for formation of first conductivity type transistors while leaving a second substrate area configured for formation of second conductivity type transistors effectively unmasked. In the one masking step, a first conductivity type well implant is conducted into the second substrate area and a second conductivity type gate implant is conducted into the transistor gate layer within the second substrate area. In another masking step after the one masking step, the second substrate area is effectively masked by a masking material and only a portion of the first substrate area is effectively masked while leaving a majority of the first substrate area effectively unmasked. With the masking material in place, a first conductivity type implant is conducted into the transistor gate layer within the first substrate area while leaving a substantially undoped region of transistor gate layer semiconductive material within the first substrate area. After conducting the first conductivity type implant into the transistor gate layer within the first substrate area, at least some of the masking material within the first substrate area is laterally etched away. After laterally etching away the masking material within the first substrate area, a second conductivity type well implant is conducted within the first substrate area.